The present invention relates to a memory embedded semiconductor device comprising a memory such as a DRAM or a ROM and a high-speed CMOS logic circuit.
A DRAM embedded LSI is an LSI having a memory region and a logic region each provided in a common substrate and suitable for processing a large amount of data at a high speed due to the structural feature thereof which allows a wider data bus to be provided between the memory and logic regions. In addition, the DRAM embedded LSI need not use wiring provided on a printed circuit board or the like which is located outside of the LSI package. This achieves a reduction in the power consumption of a system and renders the DRAM embedded LSI extremely effective as a system LSI.
To enhance the performance of a transistor (logic transistor) in the logic region of the DRAM embedded LSI, it is necessary to reduce the parasitic resistance of the transistor by using a salicide technology. However, since a shallow junction is used in each of the source/drain regions of a transistor (memory transistor) provided in the memory region with the view to suppressing a short channel effect, a leakage current to the substrate increases when a silicide layer is formed on each of the source/drain regions of the memory transistor so that a charge retention time (pause time) is shortened. A description will be given herein below to the structures of conventional DRAM embedded LSIs and fabrication methods therefor with reference to the drawings.
CONVENTIONAL EMBODIMENT 1
FIG. 3 shows a cross-sectional structure of a memory embedded semiconductor device (DRAM embedded LSI) according to a first conventional embodiment disclosed in Japanese Laid-Open Patent Publication No. 2000-332220 (Abstract).
As shown in the drawing, a memory embedded semiconductor device according to the first conventional embodiment has a logic region Rlogc comprising logic transistors and a DRAM region Rdram comprising the transistors of DRAM memory cells (memory transistors) disposed in a common semiconductor substrate 100. Although the logic transistors include a p-channel transistor and an n-channel transistor, the drawing shows only the n-channel transistor. The drawing also shows the structure in which n-channel transistors are used as the memory transistors.
The logic transistor comprises: a gate insulating film 102 and a gate electrode 103 each provided on an active region surrounded by isolations (trench isolations) 101; source/drain diffusion layers 104 formed in the regions of the semiconductor substrate 100 located sidewise of the gate electrode 103; and sidewalls 105 covering the side surfaces of the gate electrode 103. The gate electrode 103 is composed of a lower electrode 103a made of polysilicon containing an n-type impurity and an upper electrode 103b made of silicide. The upper electrode 103b is formed simultaneously with source/drain silicide layers 106 formed on the source/drain diffusion layers 104 by a common salicide process step.
Each of the memory transistors comprises: a gate insulating film 112 and a gate electrode 113 each provided on an active region surrounded by the isolations (trench isolations) 101; source/drain diffusion layers 114 formed in the regions of the semiconductor substrate 100 located sidewise of the gate electrode 113; and sidewalls 115 covering the side surfaces of the gate electrode 113. The gate electrode 113 is composed of a lower electrode 113a made of polysilicon containing an n-type impurity and an upper electrode 113b made of silicide. It is to be noted that source/drain suicide layers are not provided in the memory transistor.
CONVENTIONAL EMBODIMENT 2
FIG. 4 shows a cross-sectional structure of a memory embedded semiconductor device according to a second conventional embodiment disclosed in Japanese Laid-Open Patent Publication No. 2001-127270 (Abstract), which allows the higher-speed operation of the memory transistors.
As shown in the drawing, the memory embedded semiconductor device according to the second conventional embodiment has a logic region Rlogc and a DRAM region Rdram disposed in a common semiconductor substrate 200 in the same manner as in the first conventional embodiment.
A logic transistor comprises: a gate insulating film 202 and a gate electrode 203 each provided on an active region surrounded by isolations (trench isolations) 201; source/drain diffusion layers 204 formed in the regions of the semiconductor substrate 200 located sidewise of the gate electrode 203; and sidewalls 205 covering the side surfaces of the gate electrode 203. The gate electrode 203 is composed of a lower electrode 203a made of polysilicon containing an n-type impurity and an upper electrode 203b made of silicide. The upper electrode 203b is formed simultaneously with source/drain silicide layers 206 formed on the source/drain diffusion layers 204 by a common salicide process step.
On the other hand, a memory transistor comprises: a gate insulating film 212 and a gate electrode 213 each provided on an active region surrounded by the isolations (trench isolations) 201, source/drain diffusion layers 214 formed in the regions of the semiconductor substrate 200 located sidewise of the gate electrode 213; and sidewalls 215 covering the side surfaces of the gate electrode 213. The gate electrode 213 is composed of a lower electrode 213a made of polysilicon containing an n-type impurity and an upper electrode 213b made of silicide. The upper electrode 213b is formed simultaneously with source/drain silicide layers 216 formed on the source/drain diffusion layers 214 by a common salicide process step.
In the memory embedded semiconductor device according to the first conventional embodiment, a junction leakage can be reduced and an impurity concentration in each of the source/drain diffusion layers 114 can be reduced because the silicide layer is not formed on either of the source/drain diffusion layers 114 of the memory transistor. This provides a memory transistor with an excellent short-channel effect (with a reduced off leakage). As a result, it becomes possible to implant a logic transistor operable at a high speed, while suppressing a reduction in pause time.
In recent years, however, an ultra-high-speed operation at about 200 MHz has been requested of a memory as a replacement of an SRAM in the DRAM embedded LSI. In the memory embedded semiconductor device (DRAM embedded LSI) according to the first conventional embodiment, the problem is encountered that it is difficult to allow a high-speed operation because of the high parasitic resistance of each of the source/drain diffusion layers of the memory transistor.
By contrast, the silicide layer 216 is formed on each of the source/drain diffusion layers 214 of the memory transistor in the memory embedded semiconductor device according to the second conventional embodiment. The arrangement has achieved an impurity concentration equal to that in the logic transistor in each of the source/drain diffusion layers 214. A resulting reduction in parasitic resistance due to the silicide allows the higher-speed operation of the memory transistor and thereby implements a high-speed memory operation.
In the memory embedded semiconductor device according to the second conventional embodiment, however, the memory transistor is allowed to have only a leakage characteristic as low as that of the logic transistor so that the pause time is shortened, though the memory operation is performed. Accordingly, it becomes necessary to increase the number of times data refreshing is performed so that power consumption is increased. As a result, the problem is encountered that it is difficult to embed a DRAM having a memory capacity over 10 Mbits in terms of power consumption, though the embedding of a DRAM having a memory capacity of about 1 to 2 Mbits presents no serious problem.